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twindie? 1.2v ddr4 sdram mt40a1g16 C 64 meg x 16 x 16 banks x 1 ranks description the 16gb (twindie?) ddr4 sdram uses microns 8gb ddr4 sdram die; two x8s combined to make one x16. similar signals as mono x16, there is one extra zq connection for faster zq calibration and a bg1 control required for x8 addressing. refer to mi- crons 8gb ddr4 sdram data sheet (x8 option) for the specifications not included in this document. specifications for base part number mt40a1g8 corre- late to twindie manufacturing part number mt40a1g16. features ? uses two x8 8gb micron die to make one x16 ? single rank twindie ? v dd = v ddq = 1.2v (1.14C1.26v) ? 1.2v v ddq -terminated i/o ? jedec-standard ball-out ? low-profile package ? t c of 0c to 95c C 0c to 85c: 8192 refresh cycles in 64ms C 85c to 95c: 8192 refresh cycles in 32ms options marking ? configuration C 64 meg x 16 x 16 banks x 1 rank 1g16 ? 96-ball fbga package (pb-free) C 9.5mm x 14mm x 1.2mm die rev :a hba C 8.0mm x 14mm x 1.2mm die rev :b, d wbu C 7.5mm x 13.5mm x 1.2mm die rev :h knr ? timing C cycle time 1 C 0.682ns @ cl = 20 (ddr4-2933) -068e C 0.682ns @ cl = 21 (ddr4-2933) -068 C 0.750ns @ cl = 18 (ddr4-2666) -075e C 0.750ns @ cl = 19 (ddr4-2666) -075 C 0.833ns @ cl = 16 (ddr4-2400) -083e C 0.833ns @ cl = 17 (ddr4-2400) -083 C 0.937ns @ cl = 15 (ddr4-2133) -093e C 0.937ns @ cl = 16 (ddr4-2133) -093 C 1.071ns @ cl = 13 (ddr4-1866) -107e ? self refresh C standard none ? operating temperature C commercial (0c t c 95c) none ? revision :a :b, d :h note: 1. cl = cas (read) latency. table 1: key timing parameters speed grade data rate (mt/s) target t rcd- t rp-cl t rcd (ns) t rp (ns) cl (ns) -068e 1 2933 20-20-20 13.64 13.64 13.64 -068 1 2933 21-21-21 14.32 14.32 14.32 -075e 2 2666 18-18-18 13.5 13.5 13.5 -075 2 2666 19-19-19 14.25 14.25 14.25 -083e 3 2400 16-16-16 13.32 13.32 13.32 -083 3 2400 17-17-17 14.16 14.16 14.16 -093e 4 2133 15-15-15 14.06 14.06 14.06 -093 4 2133 16-16-16 15 15 15 -107e 5 1866 13-13-13 13.92 13.92 13.92 notes: 1. backward compatible to 1600, cl = 11; 1866, cl = 13; 2133, cl = 15; 2400, cl = 17; and 2666, cl = 19. 2. backward compatible to 1600, cl = 11; 1866, cl = 13; 2133, cl = 15; and 2400, cl = 17. 16gb: x16 twindie single rank ddr4 sdram description 09005aef86573aa8 ddr4_16gb_x16_1cs_twindie.pdf - rev. e 12/16 en 1 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved. products and specifications discussed herein are subject to change by micron without notice.
3. backward compatible to 1600, cl = 11; 1866, cl = 13; and 2133, cl = 15. 4. backward compatible to 1600, cl = 11 and 1866, cl = 13. 5. backward compatible to 1600, cl = 11. table 2: addressing parameter 1024 meg x 16 configuration 64 meg x 16 x 16 banks x 1 rank bank group address bg[1:0] bank count per group 4 bank address in bank group ba[1:0] row addressing 64k (a[15:0]) column addressing 1k (a[9:0]) page size 1kb note: 1. page size is per bank, calculated as follows: page size = 2 colbits org/8, where colbit = the number of column address bits and org = the number of dq bits. 16gb: x16 twindie single rank ddr4 sdram description 09005aef86573aa8 ddr4_16gb_x16_1cs_twindie.pdf - rev. e 12/16 en 2 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
ball assignments figure 1: 96-ball x16 sr ddp ball assignments 1 2 3 4 6 7 8 9 5 v ddq v pp v ddq v dd v ss v ssq v ddq v ssq v dd v ss v dd v refca v ss reset_n v dd v ss v ss v ssq v ss udq4 v ssq v ddq ldq0 ldq4 v ddq cke we_n/a14 bg0 bg1 ba0 a6 a8 a11 udq0 v dd udq2 udq6 v ssq ldqs_c ldqs_t ldq2 ldq6 odt act_n a10/ap a4 a0 a2 par udqs_c udqs_t udq3 udq7 ldq1 v dd ldq3 ldq7 ck_t cs_n a12/bc_n a3 a1 a9 v ssq udq1 udq5 v ssq v ssq v ddq v ss ldq5 v ddq ck_c ras_n/a16 cas-n/a15 ba1 a5 a7 a13 v ddq v dd v ssq v ddq v ddq uzq lzq v ssq v dd v ss v dd ten v pp v dd a b c d e f g h j k l m n p r t a b c d e f g h j k l m n p r t nf/ldm_n/ ldbi_n alert_n nf/udm_n/ udbi_n notes: 1. see ball descriptions in the monolithic data sheet. 2. a slash / defines a selectable function. for example: ball e2 = nf/udm_n/udbi_n where either nf, udm_n, or udbi_n is defined via mrs. 16gb: x16 twindie single rank ddr4 sdram ball assignments 09005aef86573aa8 ddr4_16gb_x16_1cs_twindie.pdf - rev. e 12/16 en 3 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
functional block diagrams figure 2: functional block diagram (128 meg x 16 x 16 banks x 1 rank) act_n cas_n/a15 ras_n/a16 we_n/a14 par vrefca ck_t ck_c ldq[7:0] ldqs_t ldqs_c a[13:0] ba[1:0] bg[1:0] byte 0 (64 meg x 8 x 16 banks) byte 1 (64 meg x 8 x 16 banks) (128 meg x 16 x 16 banks) cs_n cke odt uzq lzq udm_n/ udbi_n ldm_n/ ldbi_n ten reset_n alert_n udq[7:0] udqs_t udqs_c 16gb: x16 twindie single rank ddr4 sdram functional block diagrams 09005aef86573aa8 ddr4_16gb_x16_1cs_twindie.pdf - rev. e 12/16 en 4 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
connectivity test mode connectivity test (ct) mode for the x16 twindie single rank (sr) device is the same as two mono x8 devices connected in parallel. the mapping is restated for clarity. minimum terms definition for logic equations the test input and output pins are related by the following equations, where inv de- notes a logical inversion operation and xor a logical exclusive or operation: mt0 = xor (a1, a6, par) mt1 = xor (a8, alert_n, a9) mt2 = xor (a2, a5, a13) mt3 = xor (a0, a7, a11) mt4 = xor (ck_c, odt, cas_n/a15) mt5 = xor (cke, ras_n/a16, a10/ap) mt6 = xor (act_n, a4, ba1) mt7l = xor (bg1, ldm_n/ldbi_n, ck_t) mt7u = xor (bg1, udm_n/udbi_n, ck_t) mt8 = xor (we_n/a14, a12 / bc, ba0) mt9 = xor (bg0, a3, reset_n and ten) logic equations for a x16 twindie, sr device byte 0 byte 1 ldq0 = mt0 udq0 = mt0 ldq1 = mt1 udq1 = mt1 ldq2 = mt2 udq2 = mt2 ldq3 = mt3 udq3 = mt3 ldq4 = mt4 udq4 = mt4 ldq5 = mt5 udq5 = mt5 ldq6 = mt6 udq6 = mt6 ldq7 = mt7l udq7 = mt7u ldqs_t = mt8 udqs_t = mt8 ldqs_c = mt9 udqs_c = mt9 x16 twindie, sr internal connections the figure below shows the internal connections of the x16 twindie, sr. the diagram shows why byte 0 and byte 1 outputs have the same logic equations except ldq7 and udq7; they are different because the dm_n/dbi_n pins are not common for each byte. 16gb: x16 twindie single rank ddr4 sdram connectivity test mode 09005aef86573aa8 ddr4_16gb_x16_1cs_twindie.pdf - rev. e 12/16 en 5 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 3: x16 twindie, sr act_n cas_n/a15 ras_n/a16 we_n/a14 par v refca ck_t ck_c ldq[7:0] ldqs_t ldqs_c a[13:0] ba[1:0] bg[1:0] byte 1 cs_n cke odt uzq lzq udm_n/ udbi_n ldm_n/ ldbi_n ten reset_n alert_n udq[7:0] udqs_t udqs_c byte 0 16gb: x16 twindie single rank ddr4 sdram connectivity test mode 09005aef86573aa8 ddr4_16gb_x16_1cs_twindie.pdf - rev. e 12/16 en 6 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
electrical specifications C leakages table 3: input and output leakages symbol parameter min max units notes i i input leakage current any input 0v v in v dd , v ref pin 0v v in 1.1v (all other pins not under test = 0v) C4 4 a 1 i vref v ref supply leakage current v refdq = v dd /2 or v refca = v dd /2 (all other pins not under test = 0v) C4 4 a 2 i zq input leakage on zq pin C3 3 a i ten input leakage on ten pin C12 20 a i ozpd output leakage: v out = v ddq C 10 a 3 i ozpu output leakage: v out = v ssq C100 C a 3, 4 notes: 1. any input 0v < vin < 1.1v 2. v refca = v dd /2, v dd at valid level. 3. dqs are disabled. 4. odt is disabled with the odt input high. temperature and thermal impedance it is imperative that the ddr4 sdram devices temperature specifications, shown in the following table, be maintained in order to ensure the junction temperature is in the proper operating range to meet data sheet specifications. an important step in main- taining the proper junction temperature is using the devices thermal impedances cor- rectly. the thermal impedances listed in table 5 (page 8) apply to the current die re- vision and packages. incorrectly using thermal impedances can produce significant errors. read micron technical note tn-00-08, thermal applications, prior to using the values listed in the thermal impedance table. for designs that are expected to last several years and require the flexibility to use several dram die shrinks, consider using final target theta values (rather than existing values) to account for increased thermal impedances from the die size reduction. the ddr4 sdram devices safe junction temperature range can be maintained when the t c specification is not exceeded. in applications where the devices ambient tem- perature is too high, use of forced air and/or heat sinks may be required to satisfy the case temperature specifications. 16gb: x16 twindie single rank ddr4 sdram electrical specifications C leakages 09005aef86573aa8 ddr4_16gb_x16_1cs_twindie.pdf - rev. e 12/16 en 7 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 4: thermal characteristics notes 1C3 apply to entire table parameter symbol value units notes operating temperature t c 0 to 85 c 0 to 95 c 4 notes: 1. max operating case temperature t c is measured in the center of the package, as shown below. 2. a thermal solution must be designed to ensure that the device does not exceed the maximum t c during operation. 3. device functionality is not guaranteed if the device exceeds maximum t c during operation. 4. if t c exceeds 85c, the dram must be refreshed externally at 2x refresh, which is a 3.9s interval refresh rate. the use of self refresh temperature (srt) or automatic self refresh (asr), if available, must be enabled. figure 4: temperature test point location test point length (l) width (w) 0.5 (w) 0.5 (l) table 5: thermal impedance die rev. substrate conductivity ja (c/w) airflow = 0m/s ja (c/w) airflow = 1m/s ja (c/w) airflow = 2m/s jb (c/w) jc (c/w) notes a low tbd tbd tbd n/a tbd 1 high tbd tbd tbd tbd n/a b, d low 43.9 33.0 29.5 n/a 3.3 1 high 27.1 21.7 20.1 10.5 n/a h low tbd tbd tbd n/a tbd 1 high tbd tbd tbd tbd n/a note: 1. thermal resistance data is based on a number of samples from multiple lots and should be viewed as a typical number. 16gb: x16 twindie single rank ddr4 sdram electrical specifications C leakages 09005aef86573aa8 ddr4_16gb_x16_1cs_twindie.pdf - rev. e 12/16 en 8 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
dram package electrical specifications table 6: dram package electrical specifications for x16 devices notes 1C4 apply to the entire table parameter symbol ddr4-1600, -1866 ddr4-2133, -2400 ddr4-2666, -2933 unit notes min max min max min max input/ output zpkg z io 30 50 30 50 30 50 ohm 5, 6 package delay td io 65 120 65 120 65 120 ps 6 , 7 lpkg l io C 5.0 C 5.0 C 5.0 nh cpkg c io C 3.0 C 3.0 C 3.0 pf dqsl_t/ dqsl_c/ dqsu_t/ dqsu_c zpkg z io dqs 30 50 30 50 30 50 ohm 5 package delay td io dqs 65 120 65 120 65 120 ps 7 lpkg l io dqs C 5.0 C 5.0 C 5.0 nh cpkg c io dqs C 3.0 C 3.0 C 3.0 pf dqsl_t/ dqsl_c, dqsu_t/ dqsu_c, delta zpkg dz io dqs C 20 C 20 C 20 ohm 5, 8 delta delay dtd io dqs C 45 C 45 C 45 ps 7, 8 input ctrl pins zpkg z i ctrl 35 65 35 65 35 65 ohm 5, 9 package delay td i ctrl 75 120 75 120 75 120 ps 7, 9 lpkg l i ctrl C 6.5 C 6.5 C 6.5 nh cpkg c i ctrl C 2.5 C 2.5 C 2.5 pf input cmd add pins zpkg z i add cmd 35 65 35 65 35 65 ohm 5, 10 package delay td i add cmd 70 125 70 125 70 125 ps 7, 10 lpkg l i add cmd C 6.5 C 6.5 C 6.5 nh cpkg c i add cmd C 3.0 C 3.0 C 3.0 pf ck_t, ck_c zpkg z ck 30 55 30 55 30 55 ohm 5 package delay td ck 80 135 80 135 80 135 ps 7 delta zpkg dz dck C 0.5 C 0.5 C 0.5 ohm 5, 11 delta delay dtd dck C 1.2 C 1.2 C 1.2 ps 7, 11 input clk lpkg l i clk C 6.0 C 6.0 C 6.0 nh cpkg c i clk C 3.0 C 3.0 C 3.0 pf zq zpkg z o zq C 40 C 40 C 40 ohm 5 zq delay td o zq 55 120 55 120 55 120 ps 7 alert zpkg z o alert 30 55 30 55 30 55 ohm 5 alert delay td o alert 65 110 65 110 65 110 ps 7 notes: 1. the package parasitic (l and c) are not subject to production testing. if the package par- asitic (l and c) are measured, the capacitance is measured with v dd , v ddq , v ss , and v ssq shorted with all other signal pins floating. the inductance is measured with v dd , v ddq , v ss , and v ssq shorted and all other signal pins shorted at the die, not pin, side. 2. package implementations should satisfy targets if the zpkg and package delay fall with- in the ranges shown, and the maximum lpkg and cpkg do not exceed the maximum 16gb: x16 twindie single rank ddr4 sdram dram package electrical specifications 09005aef86573aa8 ddr4_16gb_x16_1cs_twindie.pdf - rev. e 12/16 en 9 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
values shown. the package design targets are provided for reference, system signal sim- ulations should not use these values but use the micron package model. 3. it is assumed that lpkg can be approximated as lpkg = z o td. 4. it is assumed that cpkg can be approximated as cpkg = td/z o . 5. package-only impedance (zpkg) is calculated based on the lpkg and cpkg total for a given pin where: zpkg (total per pin) = sqrt (lpkg/cpkg). 6. z io and td io apply to dq, dm, dqs_c, dqs_t, tdqs_t, and tdqs_c. 7. package-only delay (tpkg) is calculated based on lpkg and cpkg total for a given pin where: tdpkg (total per pin) = sqrt (lpkg cpkg). 8. absolute value of zio (dqs_t), zio (dqs_c) for impedance (z) or absolute value of tdio (dqs_t), tdio (dqs_c) for delay (td). 9. z i ctrl and td i ctrl apply to odt, cs_n, and cke. 10. z i add cmd and td i add cmd apply to a[17:0], ba[1:0], bg[1:0], ras_n cas_n, and we_n. 11. absolute value of zck_t, zck_c for impedance (z) or absolute value of tdck_t, tdck_c for delay (td). table 7: pad input/output capacitance parameter symbol ddr4-1600, -1866, -2133 ddr4-2400, -2666 ddr4-2933 unit notes min max min max min max input/output capacitance: dq, dm, dqs_t, dqs_c, tdqs_t, tdqs_c c io 1.8 2.8 1.8 2.8 1.8 2.8 pf 1, 2, 3 input capacitance: ck_t and ck_c c ck 2.1 2.9 2.1 2.9 2.1 2.9 pf 1, 2, 3, 4 input capacitance delta: ck_t and ck_c c dck 0 0.05 0 0.05 0 0.05 pf 1, 2, 3, 5 input/output capacitance delta: dqs_t and dqs_c c ddqs 0 0.05 0 0.05 0 0.05 pf 1, 3 input capacitance: ctrl, add, cmd input-only pins c i 1.6 2.6 1.6 2.6 1.6 2.6 pf 1, 3, 6 input capacitance delta: all ctrl input-only pins c di_ctrl C0 .9 0.9 C0 .9 0.9 C0 .9 0.9 pf 1, 3, 7 input capacitance delta: all add/cmd input-only pins c di_add_cmd C0 .9 0.9 C0 .9 0.9 C0 .9 0.9 pf 1, 3, 8, 9 input/output capacitance delta: dq, dm, dqs_t, dqs_c, tdqs_t, tdqs_c c dio C0.16 0.16 C0.16 0.16 C0.16 0.16 pf 1, 2, 10, 11 input/output capacitance: alert pin c alert 1.1 2.3 1.1 2.3 1.1 2.3 pf 1, 3 input/output capacitance: zq pin c zq C 3.7 C 3.7 C 3.7 pf 1, 3, 12 input/output capacitance: ten pin c ten 0.2 2.3 0.2 2.3 0.2 2.3 pf 1, 3, 13 notes: 1. although the dm, tdqs_t, and tdqs_c pins have different functions, the loading matches dq and dqs. 16gb: x16 twindie single rank ddr4 sdram dram package electrical specifications 09005aef86573aa8 ddr4_16gb_x16_1cs_twindie.pdf - rev. e 12/16 en 10 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
2. this parameter is not subject to a production test; it is verified by design and characteri- zation and are provided for reference; system signal simulations should not use these values but use the micron package model. the capacitance, if and when, is measured ac- cording to the jep147 specification, procedure for measuring input capacitance using a vector network analyzer (vna), with v dd , v ddq , v ss , and v ssq applied and all other pins floating (except the pin under test, cke, reset_n and odt, as necessary). v dd = v ddq = 1.5v, v bias = v dd /2 and on-die termination off. 3. this parameter applies to sr x16 twindie, obtained by de-embedding the package l and c parasitics. 4. c dio = c io (dq, dm) - 0.5 (c io (dqs_t) + c io (dqs_c)). 5. absolute value of c io (dqs_t), c io (dqs_c) 6. absolute value of cck_t, cck_c 7. c i applies to odt, cs_n, cke, a[15:0], ba[1:0], ras_n, cas_n, and we_n. 8. c di_ctrl applies to odt, cs_n, and cke. 9. c di_ctrl = c i (ctrl) - 0.5 (c i (clk_t) + c i (clk_c)). 10. c di_add_cmd applies to a[15:0], ba1:0], ras_n, cas_n and we_n. 11. c di_add_cmd = c i (add_cmd) - 0.5 (c i (clk_t) + c i (clk_c)). 12. maximum external load capacitance on zq pin: 5pf. 13. only applicable if ten pin does not have an internal pull-up. 16gb: x16 twindie single rank ddr4 sdram dram package electrical specifications 09005aef86573aa8 ddr4_16gb_x16_1cs_twindie.pdf - rev. e 12/16 en 11 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
current specifications C limits table 8: x16 i dd , i pp , and i ddq current limits C rev. a symbol ddr4-2133 1 ddr4-2400 ddr4-2666 ddr4-2933 unit notes i dd0 : one bank activate-to-precharge current 110 120 130 tbd ma 2, 3, 4 i pp0 : one bank activate-to-precharge i pp current 6 6 6 tbd ma i dd1 : one bank activate-to-read-to-pre- charge current 140 150 160 tbd ma 3, 4, 5 i dd2n : precharge standby current 90 100 110 tbd ma 4, 6, 7, 8, 9, 10, 11 i dd2nt : precharge standby odt current 110 120 130 tbd ma 4, 11 i dd2p : precharge power-down current 50 60 70 tbd ma 4, 11 i dd2q : precharge quiet standby current 90 90 100 tbd ma 4, 11 i dd3n : active standby current 110 110 120 tbd ma 4, 11 i pp3n : active standby i pp current 6 6 6 tbd ma i dd3p : active power-down current 70 80 80 tbd ma 4, 11 i dd4r : burst read current 300 300 350 tbd ma 4, 14, 13, 11 i dd4w : burst write current 300 320 350 tbd ma 4, 11, 15, 16, 17, 18 i dd5b : burst refresh current (1x ref) 450 450 450 tbd ma 4, 19, 20 i pp5b : burst refresh i pp current (1x ref) 60 60 60 tbd ma i dd6n : self refresh current; 0C85c 60 60 60 tbd ma 11, 21 i dd6e : self refresh current; 0C95c 70 70 70 tbd ma 11, 22 i dd6r : self refresh current; 0C45c 50 50 50 tbd ma 11, 23, 24 i dd6a : auto self refresh current (25c) 40 40 40 tbd ma 11, 24 i dd6a : auto self refresh current (45c) 50 50 50 tbd ma 11, 24 i dd6a : auto self refresh current (75c) 70 70 70 tbd ma 11, 24 i dd7 : bank interleave read current 400 410 430 tbd ma 4 i pp7 : bank interleave read i pp current 30 30 30 tbd ma i dd8 : maximum power-down current 40 40 40 tbd ma 11 notes: 1. ddr4-1600 and ddr4-1866 use the same i dd limits as ddr4-2133. 2. when additive latency is enabled for i dd0 , current changes by approximately 0%. 3. i pp0 test and limit is applicable for i dd0 and i dd1 conditions. 4. the i dd values must be derated (increased) when operated outside of the range 0c t c 85c: when t c < 0c: i dd2p and i dd3p must be derated by 6%; i dd4r and i dd4w must be derated by 4%; and i dd7 must be derated by 11%. 16gb: x16 twindie single rank ddr4 sdram current specifications C limits 09005aef86573aa8 ddr4_16gb_x16_1cs_twindie.pdf - rev. e 12/16 en 12 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
when t c > 85c: i dd0 , i dd1 , i dd2n , i dd2nt , i dd2q , i dd3n , i dd3p , i dd4r , i dd4w , and i dd5b must be derated by 3%; i dd2p must be derated by 40%. 5. when additive latency is enabled for i dd1 , current changes by approximately +4%. 6. when additive latency is enabled for i dd2n , current changes by approximately +0%. 7. when dll is disabled for i dd2n , current changes by approximately C23%. 8. when cal is enabled for i dd2n , current changes by approximately C25%. 9. when gear-down is enabled for i dd2n , current changes by approximately 0%. 10. when ca parity is enabled for i dd2n , current changes by approximately +7%. 11. i pp3n test and limit is applicable for all i dd2x , i dd3x , i dd4x , i dd6x , and i dd8 conditions; that is, testing i pp3n should satisfy the i pp s for the noted i dd tests. 12. when additive latency is enabled for i dd3n , current changes by approximately +0.6%. 13. when additive latency is enabled for i dd4r , current changes by approximately +5%. 14. when read dbi is enabled for i dd4r , current changes by approximately 0%. 15. when additive latency is enabled for i dd4w , current changes by approximately +4%. 16. when write dbi is enabled for i dd4w , current changes by approximately 0%. 17. when write crc is enabled for i dd4w , current changes by approximately C3%. 18. when ca parity is enabled for i dd4w , current changes by approximately +12%. 19. when 2x ref is enabled for i dd5b , current changes by approximately C14%. 20. when 4x ref is enabled for i dd5b , current changes by approximately C33%. 21. applicable for mr2 settings a7 = 0 and a6 = 0; manual mode with normal temperature range of operation (0C85c). 22. applicable for mr2 settings a7 = 1 and a7 = 0; manual mode with extended tempera- ture range of operation (0C95c). 23. applicable for mr2 settings a7 = 0 and a7 = 1; manual mode with reduced temperature range of operation (0C45c). 24. i dd6r and i dd6a values are typical. table 9: x16 i dd , i pp , and i ddq current limits C rev. b, d symbol ddr4-2133 1 ddr4-2400 ddr4-2666 ddr4-2933 unit notes i dd0 : one bank activate-to-precharge current 90 96 102 108 ma 2, 3, 4 i pp0 : one bank activate-to-precharge i pp current 6 6 6 6 ma i dd1 : one bank activate-to-read-to-pre- charge current 114 120 126 132 ma 3, 4, 5 i dd2n : precharge standby current 66 68 70 72 ma 4, 6, 7, 8, 9, 10, 11 i dd2nt : precharge standby odt current 90 100 100 110 ma 4, 11 i dd2p : precharge power-down current 50 50 50 50 ma 4, 11 i dd2q : precharge quiet standby current 60 60 60 60 ma 4, 11 i dd3n : active standby current 80 86 92 98 ma 4, 11 i pp3n : active standby i pp current 6 6 6 6 ma i dd3p : active power-down current 78 82 86 90 ma 4, 11 i dd4r : burst read current 250 270 292 314 ma 4, 14, 13, 11 16gb: x16 twindie single rank ddr4 sdram current specifications C limits 09005aef86573aa8 ddr4_16gb_x16_1cs_twindie.pdf - rev. e 12/16 en 13 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
table 9: x16 i dd , i pp , and i ddq current limits C rev. b, d (continued) symbol ddr4-2133 1 ddr4-2400 ddr4-2666 ddr4-2933 unit notes i dd4w : burst write current 230 246 264 282 ma 4, 11, 15, 16, 17, 18 i dd5b : burst refresh current (1x ref) 500 500 500 500 ma 4, 19, 20 i pp5b : burst refresh i pp current (1x ref) 56 56 56 56 ma i dd6n : self refresh current; 0C85c 60 60 60 60 ma 11, 21 i dd6e : self refresh current; 0C95c 70 70 70 70 ma 11, 22 i dd6r : self refresh current; 0C45c 40 40 40 40 ma 11, 23, 24 i dd6a : auto self refresh current (25c) 17.2 17.2 17.2 17.2 ma 11, 24 i dd6a : auto self refresh current (45c) 40 40 40 40 ma 11, 24 i dd6a : auto self refresh current (75c) 60 60 60 60 ma 11, 24 i dd7 : bank interleave read current 340 350 360 370 ma 4 i pp7 : bank interleave read i pp current 30 30 30 30 ma i dd8 : maximum power-down current 50 50 50 50 ma 11 notes: 1. ddr4-1600 and ddr4-1866 use the same i dd limits as ddr4-2133. 2. when additive latency is enabled for i dd0 , current changes by approximately 0%. 3. i pp0 test and limit is applicable for i dd0 and i dd1 conditions. 4. the i dd values must be derated (increased) when operated outside of the range 0c t c 85c: when t c < 0c: i dd2p and i dd3p must be derated by 6%; i dd4r and i dd4w must be derated by 4%; and i dd7 must be derated by 11%. when t c > 85c: i dd0 , i dd1 , i dd2n , i dd2nt , i dd2q , i dd3n , i dd3p , i dd4r , i dd4w , and i dd5b must be derated by 3%; i dd2p must be derated by 40%. 5. when additive latency is enabled for i dd1 , current changes by approximately +4%. 6. when additive latency is enabled for i dd2n , current changes by approximately +0%. 7. when dll is disabled for i dd2n , current changes by approximately C23%. 8. when cal is enabled for i dd2n , current changes by approximately C25%. 9. when gear-down is enabled for i dd2n , current changes by approximately 0%. 10. when ca parity is enabled for i dd2n , current changes by approximately +7%. 11. i pp3n test and limit is applicable for all i dd2x , i dd3x , i dd4x , i dd6x , and i dd8 conditions; that is, testing i pp3n should satisfy the i pp s for the noted i dd tests. 12. when additive latency is enabled for i dd3n , current changes by approximately +0.6%. 13. when additive latency is enabled for i dd4r , current changes by approximately +5%. 14. when read dbi is enabled for i dd4r , current changes by approximately 0%. 15. when additive latency is enabled for i dd4w , current changes by approximately +4%. 16. when write dbi is enabled for i dd4w , current changes by approximately 0%. 17. when write crc is enabled for i dd4w , current changes by approximately C3%. 18. when ca parity is enabled for i dd4w , current changes by approximately +12%. 19. when 2x ref is enabled for i dd5b , current changes by approximately C14%. 20. when 4x ref is enabled for i dd5b , current changes by approximately C33%. 21. applicable for mr2 settings a7 = 0 and a6 = 0; manual mode with normal temperature range of operation (0C85c). 16gb: x16 twindie single rank ddr4 sdram current specifications C limits 09005aef86573aa8 ddr4_16gb_x16_1cs_twindie.pdf - rev. e 12/16 en 14 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
22. applicable for mr2 settings a7 = 1 and a7 = 0; manual mode with extended tempera- ture range of operation (0C95c). 23. applicable for mr2 settings a7 = 0 and a7 = 1; manual mode with reduced temperature range of operation (0C45c). 24. i dd6r and i dd6a values are typical. table 10: x16 i dd , i pp , and i ddq current limits C rev. h symbol ddr4-2133 1 ddr4-2400 ddr4-2666 ddr4-2933 unit notes i dd0 : one bank activate-to-precharge current tbd tbd tbd tbd ma 2, 3, 4 i pp0 : one bank activate-to-precharge i pp current tbd tbd tbd tbd ma i dd1 : one bank activate-to-read-to-pre- charge current tbd tbd tbd tbd ma 3, 4, 5 i dd2n : precharge standby current tbd tbd tbd tbd ma 4, 6, 7, 8, 9, 10, 11 i dd2nt : precharge standby odt current tbd tbd tbd tbd ma 4, 11 i dd2p : precharge power-down current tbd tbd tbd tbd ma 4, 11 i dd2q : precharge quiet standby current tbd tbd tbd tbd ma 4, 11 i dd3n : active standby current tbd tbd tbd tbd ma 4, 11 i pp3n : active standby i pp current tbd tbd tbd tbd ma i dd3p : active power-down current tbd tbd tbd tbd ma 4, 11 i dd4r : burst read current tbd tbd tbd tbd ma 4, 14, 13, 11 i dd4w : burst write current tbd tbd tbd tbd ma 4, 11, 15, 16, 17, 18 i dd5b : burst refresh current (1x ref) tbd tbd tbd tbd ma 4, 19, 20 i pp5b : burst refresh i pp current (1x ref) tbd tbd tbd tbd ma i dd6n : self refresh current; 0C85c tbd tbd tbd tbd ma 11, 21 i dd6e : self refresh current; 0C95c tbd tbd tbd tbd ma 11, 22 i dd6r : self refresh current; 0C45c tbd tbd tbd tbd ma 11, 23, 24 i dd6a : auto self refresh current (25c) tbd tbd tbd tbd ma 11, 24 i dd6a : auto self refresh current (45c) tbd tbd tbd tbd ma 11, 24 i dd6a : auto self refresh current (75c) tbd tbd tbd tbd ma 11, 24 i dd7 : bank interleave read current tbd tbd tbd tbd ma 4 i pp7 : bank interleave read i pp current tbd tbd tbd tbd ma i dd8 : maximum power-down current tbd tbd tbd tbd ma 11 notes: 1. ddr4-1600 and ddr4-1866 use the same i dd limits as ddr4-2133. 2. when additive latency is enabled for i dd0 , current changes by approximately 0%. 3. i pp0 test and limit is applicable for i dd0 and i dd1 conditions. 16gb: x16 twindie single rank ddr4 sdram current specifications C limits 09005aef86573aa8 ddr4_16gb_x16_1cs_twindie.pdf - rev. e 12/16 en 15 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
4. the i dd values must be derated (increased) when operated outside of the range 0c t c 85c: when t c < 0c: i dd2p and i dd3p must be derated by 6%; i dd4r and i dd4w must be derated by 4%; and i dd7 must be derated by 11%. when t c > 85c: i dd0 , i dd1 , i dd2n , i dd2nt , i dd2q , i dd3n , i dd3p , i dd4r , i dd4w , and i dd5b must be derated by 3%; i dd2p must be derated by 40%. 5. when additive latency is enabled for i dd1 , current changes by approximately +4%. 6. when additive latency is enabled for i dd2n , current changes by approximately +0%. 7. when dll is disabled for i dd2n , current changes by approximately C23%. 8. when cal is enabled for i dd2n , current changes by approximately C25%. 9. when gear-down is enabled for i dd2n , current changes by approximately 0%. 10. when ca parity is enabled for i dd2n , current changes by approximately +7%. 11. i pp3n test and limit is applicable for all i dd2x , i dd3x , i dd4x , i dd6x , and i dd8 conditions; that is, testing i pp3n should satisfy the i pp s for the noted i dd tests. 12. when additive latency is enabled for i dd3n , current changes by approximately +0.6%. 13. when additive latency is enabled for i dd4r , current changes by approximately +5%. 14. when read dbi is enabled for i dd4r , current changes by approximately 0%. 15. when additive latency is enabled for i dd4w , current changes by approximately +4%. 16. when write dbi is enabled for i dd4w , current changes by approximately 0%. 17. when write crc is enabled for i dd4w , current changes by approximately C3%. 18. when ca parity is enabled for i dd4w , current changes by approximately +12%. 19. when 2x ref is enabled for i dd5b , current changes by approximately C14%. 20. when 4x ref is enabled for i dd5b , current changes by approximately C33%. 21. applicable for mr2 settings a7 = 0 and a6 = 0; manual mode with normal temperature range of operation (0C85c). 22. applicable for mr2 settings a7 = 1 and a7 = 0; manual mode with extended tempera- ture range of operation (0C95c). 23. applicable for mr2 settings a7 = 0 and a7 = 1; manual mode with reduced temperature range of operation (0C45c). 24. i dd6r and i dd6a values are typical. 16gb: x16 twindie single rank ddr4 sdram current specifications C limits 09005aef86573aa8 ddr4_16gb_x16_1cs_twindie.pdf - rev. e 12/16 en 16 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
package dimensions figure 5: 96-ball fbga die rev. a (package code hba) seating plane 0.12 a ball a1 id (covered by sr) ball a1 id a 0.34 0.05 1.1 0.1 6.4 ctr 9.5 0.1 0.8 typ 12 ctr 14 0.1 96x ?0.47 dimensions apply to solder balls post- reflow on ?0.42 smd ball pads. 0.8 typ 1 2 3 7 8 9 a b c d e f g h j k l m n p r t notes: 1. all dimensions are in millimeters. 2. solder ball material: sac302 (96.8% sn, 3% ag, 0.2% cu). 16gb: x16 twindie single rank ddr4 sdram package dimensions 09005aef86573aa8 ddr4_16gb_x16_1cs_twindie.pdf - rev. e 12/16 en 17 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 6: 96-ball fbga die rev. b (package code wbu) seating plane 0.12 a ball a1 id (covered by sr) ball a1 id a 0.34 0.05 1.1 0.1 6.4 ctr 8 0.1 0.8 typ 12 ctr 14 0.1 96x ?0.47 dimensions apply to solder balls post- reflow on ?0.42 smd ball pads. 0.8 typ 1 2 3 7 8 9 a b c d e f g h j k l m n p r t notes: 1. all dimensions are in millimeters. 2. solder ball material: sac302 (96.8% sn, 3% ag, 0.2% cu). 16gb: x16 twindie single rank ddr4 sdram package dimensions 09005aef86573aa8 ddr4_16gb_x16_1cs_twindie.pdf - rev. e 12/16 en 18 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.
figure 7: 96-ball fbga die rev. h (package code knr) seating plane ball a1 id (covered by sr) ball a1 id 0.34 0.05 1.1 0.1 6.4 ctr 7.5 0.1 0.8 typ 12 ctr 13.5 0.1 96x ? 0.47 dimensions apply to solder balls post- reflow on ? 0.42 smd ball pads. 0.8 typ 1 2 3 7 8 9 a b c d e f g h j k l m n p r t a 0.12 a notes: 1. all dimensions are in millimeters. 2. solder ball material: sac302 (96.8% sn, 3% ag, 0.2% cu). 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-4000 www.micron.com/products/support sales inquiries: 800-932-4992 micron and the micron logo are trademarks of micron technology, inc. twindie is a trademark of micron technology, inc. all other trademarks are the property of their respective owners. this data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein. although considered final, these specifications are subject to change, as further product development and data characterization some- times occur. 16gb: x16 twindie single rank ddr4 sdram package dimensions 09005aef86573aa8 ddr4_16gb_x16_1cs_twindie.pdf - rev. e 12/16 en 19 micron technology, inc. reserves the right to change products or specifications without notice. ? 2015 micron technology, inc. all rights reserved.

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